The present invention is related to switching devices. More particularly, the present invention provides a structure and a method for forming non-volatile resistive switching memory devices characterized by a suppression of current at low bias and a high measured ON/OFF resistance ratio.
The success of semiconductor devices has been mainly driven by an intensive transistor down-scaling process. However, as field effect transistors (FET) approach sizes less than 100 nm, problems such as short channel effect start to prevent proper device operation. Moreover, such sub 100 nm device size can lead to sub-threshold slope non-scaling and increased power dissipation. It is generally believed that transistor based memories such as those commonly known as Flash memory may approach an end to scaling within a decade. Flash memory is one type of non-volatile memory device.
Other non-volatile random access memory (RAM) devices such as ferroelectric RAM (Fe RAM), magneto-resistive RAM (MRAM), organic RAM (ORAM), and phase change RAM (PCRAM), among others, have been explored as next generation memory devices. These devices often require new materials and device structures to couple with silicon based devices to form a memory cell, which lack one or more key attributes. For example, Fe-RAM and MRAM devices have fast switching characteristics and good programming endurance, but their fabrication is not CMOS compatible and size is usually large. Switching for a PCRAM device uses joules heating, which inherently has high power consumption. Organic RAM or ORAM is incompatible with large volume silicon based fabrication and device reliability is usually poor.
As integration of memory devices increases, the size of elements is reduced while the density of elements in a given area is increased. As a result, dark current of leakage current becomes more of a problem, where leakage current can return a false result for a read operation or cause an unintentional state change in a cell. The problem of leakage current is particularly acute in two-terminal devices, in which multiple memory cells can form leakage paths through interconnecting top and bottom electrodes.
Conventional approaches to suppressing leakage current in switching devices include coupling a vertical diode to a memory element. However, the external diode approach has several disadvantages. In general, the diode fabrication process is a high temperature process, typically conducted above 500 degrees Celsius. Because most diodes rely on a P/N junction, it is difficult to scale the diode height to achieve a memory and diode structure with a desirable aspect ratio. And finally, a conventional diode is only compatible with a unipolar switching device, and not a two-way bipolar device. It is therefore desirable to have a robust and scalable method and structure for a highly integrated memory that is not adversely affected by leak currents.